Field-Programmable Gate Arrays (MA-INF 4307)

First Meeting: Thu, April 14th 10:30 in Room I.42 (LBH, Friedrich-Ebert-Allee 144). If you're interested, please send an email to
lehre@ti.uni-bonn.de.

Supervisor: Prof. Dr. Joachim K. Anlauf
Organization: Sebastian Schüller
Weekly Meeting: Mon 10:30 - 12:00, Room I.42, LBH

Prerequisites:

• Successful completion of the Lecture Dynamical Reconfigurable Systems - or -
• design skills in VHDL and knowledge of hardware design methodologies.

Content:

In the lab, you will learn how to accelerate algorithms by implementing them in reconfigurable hardware
designs on FPGAs. In the meetings we discuss the details of the problem and figure out how the algorithm
can be realized in custom hardware. You will implement the hardware design in VHDL, simulate its behaviour
and test it on actual hardware.

Feature detection is a common task in computer vision and machine learning scenarios and are increasingly used
in embedded scenarios like mobile robotics or IoT applications. In these domains, power is a limited resource and
makes more classical GPU-based hardware acceleration difficult to use.
We take a look at the FAST and BRIEF algorithm, discuss how they can be implemented in custom hardware and
create an implementation for FPGAs.