Dynamically Reconfigurable Systems (B,C) (MA-INF 4207)
Architecture of FPGAs, Configurable Logic Blocks, Wiring Ressources, Special Blocks, Hardware Description Languages, Synthesis, Technology Mapping, Place and Route, Partial Reconfigurability
Note: The lecture has been rescheduled to Tuesdays 12:45 pm - 2:15 pm
Lecturer: Prof. Dr. Joachim K. Anlauf
Time/Date: Tuesday 12:45 - 14:15 (s.t.)
Lecture Hall: HS III.03a, LBH Friedrich-Ebert Allee 144
Exercises
Monday 12:30 - 14:00 (s.t.) room E.23, LBH
Thursday 10:30 - 12:00 (s.t.) room E.23 LBH Canceled due to limited participation
Organization: Sebastian Schüller
Tutor: Annika Pick
First Tutorial: 05/11
Slides
| 1 Slide / Page | 4 Slides / Page | Contents | Date |
| 001-012 | 001-012 | Preliminaries | 04/26 |
| 013-018 | 013-018 | Introduction and Motivation | 04/26 |
| Basics of Digital Design | 05/09 | ||
| Introduction to VHDL and SystemC | 05/09 |
Exercise Sheets
| Exercise | Contents | Submission Date | |
| Sheet 1 | Combinatorial Circuits | 05/09 | |
| Sheet 2 | Sequential Circuits | 05/16 | |
| Sheet 3 | modelsim_ex.zip | VHDL | 05/23 |
Resources
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Virtex-5 FPGA Packaging and Pinout Specification
Virtex-5 FPGA XtremeDSP Design Considerations
Virtex-5 Libraries Guide for HDL Designs