Field-Programmable Gate Arrays (MA-INF 4307)

Contents

• VHDL for Hardware Description, Simulation, and Synthesis
• SystemC for Hardware Description, Simulation, and Synthesis
• Synthesizable Subsets
• Test of Implementations on FPGA Evaluation Boards

Pre-meeting

• Thursday, April 14th at 10:30 am in seminar room I.42 (Landesbehördenhaus (LBH), Friedrich-Ebert-Allee 144)
• If you are interested in attending this lab, please send us an email.

Date of meeting

• Thursdays at 10:30 am in seminar room I.42.

Exercises

• Week 1
• Week 2
• Week 3 (AKModule, Folien)

Project

• Assignment

VHDL

• You can find information about VHDL at our "VHDL Corner".

SystemC

• You can find information about SystemC at our "SystemC Corner".

Contact

• Email: pg@ti.uni-bonn.de