Dynamically Reconfigurable Systems (B,C) (MA-INF 4207)
Lecture - Summer term 2016
News:
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Lecture period
- Tuesdays 12:45-14:15 in lecture room HS III.03a (LBH, "Landesbehördenhaus")
Contents
Architecture of FPGAs, Configurable Logic Blocks, Wiring Ressources, Special Blocks, Hardware Description Languages, Synthesis, Technology Mapping, Place and Route, Partial Reconfigurability
Slides
Note: The pdf-files contain the slides as they have been presented in the lecture. Further explanations and remarks on the blackboard which have been presented in the lectue are not included. The slides can therefore only serve as memory hook.
Tutorials
- Mondays, 10:30 a.m.-12:00 a.m. (s.t.) in room E.23 (LBH)
- Tutor: Oguzhan Sezenlik
- First tutorial takes place on May 2nd
| 1 Slide per Page | 4 Slides per Page | Contents (Date of Last Change) |
| 001-012 | 001-012 | Preliminaries (4/19/2016) |
| 013-018 | 013-018 | 1. Introduction and Motivation (4/19/2016) |
| 019-037 | 019-037 | 2. Basics of Digital Design (4/19/2016) |
| 038-120 | 038-120 | 3. Introduction to VHDL and SystemC (5/3/2016) |
| 121-145 | 121-145 | 4. Programmable Logic Devices (6/6/2016) |
| 146-234 | 146-234 | 5. Architecture of FPGAs (7/5/2016) |
| 235-257 | 235-257 | 6. Design Flow (7/5/2016) |
Exercise Sheets
- Sheet 1
- Sheet 2
- Sheet 3 (attached file: exercise03.zip)
- Sheet 4
- Sheet 5 (attached file: exercise05.zip)
- Sheet 6
- Sheet 7
- Sheet 8
Resources
- Virtex-5 FPGA Family Overview
- Virtex-5 FPGA User Guide
- Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
- Virtex-5 FPGA Packaging and Pinout Specification
- Virtex-5 FPGA XtremeDSP Design Considerations
- Virtex-5 Libraries Guide for HDL Designs
- XST User Guide
Examination
- (to be announced)
Contact
- E-Mail: lehre@ti.uni-bonn.de