Dynamically Reconfigurable Systems (B,C) (MA-INF 4207)


Lecturer: Prof. Dr. Joachim K. Anlauf
Time/Date: Tuesday 12:15-13:45 (s.t.) 12:30-14:00
First Lecture: Tuesday, April 9
Lecture Hall: HS4, HSZ Campus Poppelsdorf, Endenicher Allee 19c

 

Exercises

Thursday 08-10, Room 0.011, Endenicher Allee 19A
Thursday 10-12, Room 0.011, Endenicher Allee 19A

Organization: Sebastian Schüller
Tutor:
Martin Schmidt
First Tutorial: Thursday, April 18

 

Slides

1 Slide / Page 4 Slides / Page Contents Date
1-11 1-11  Preliminaries 4/9/2019
12-17 12-17 1. Introduction and Motivation 4/9/2019
18-38 18-38 2. Basics of Digital Design

4/9/2019

39-110 39-110 3. Introduction to VHDL

5/14/2019

111-135 111-135 4. Programmable Logic Devices

5/14/2019

136-184 136-184 5. Architecture of FPGAs

6/4/2019

 Exercise Sheets

Exercise   Contents Submission Date
Sheet 1   Sequential Circuits / FSM 04/23/2019
Sheet 2   Combinatorial Circuits / FSM 04/18/2019 during the exercise
Sheet 3 exercise_03.zip ModelSim installation 04/30/2019
Sheet 4   VHDL Programming Styles 05/07/2019
Sheet 5 exercise_05.zip VHDL Testbench / Physical Types 05/14/2019
Sheet 6 exercise_06.zip VHDL  05/21/2019
Sheet 7   PLAs / PALs 06/04/2019
Sheet 8 exercise_08.zip LUTs / CLBs / Slices 06/25/2019



Resources

Ultrascale CLB User Guide

Ultrascale DSP User Guide

Ultrascale Memory Resources User Guide

Ultrascale Clocking Resources User Guide

Ultrascale Configuration User Guide