Dynamically Reconfigurable Systems (B,C) (MA-INF 4207)
Architecture of FPGAs, Configurable Logic Blocks, Wiring Ressources, Special Blocks, Hardware Description Languages, Synthesis, Technology Mapping, Place and Route, Partial Reconfigurability
Lecturer: Prof. Dr. Joachim K. Anlauf
Time/Date: Tuesday 12:30-14:00 (s.t.)
Lecture Hall: HS4, HSZ Campus Poppelsdorf, Endenicher Allee 19c
Organization of Oral Re-Examinations on 26th of September
Please select an examination time slot in the Re-Examination-Doodle
Exercises
Thursday 08-10, Room 0.011, Endenicher Allee 19A
Thursday 10-12, Room 0.011, Endenicher Allee 19A Merged with first exercise slot.
Organization: Sebastian Schüller
Tutor: Thomas Scheurich
First Tutorial: Thursday, April 26
Slides
1 Slide / Page | 4 Slides / Page | Contents | Date |
1-11 | 1-11 | Preliminaries | 4/17/2018 |
12-17 | 12-17 | 1. Introduction and Motivation | 4/16/2018 |
18-38 | 18-38 | 2. Basics of Digital Design |
4/24/2018 |
39-108 | 39-108 | 3. Introduction to VHDL |
5/7/2018 |
109-133 | 109-133 | 4. Programmable Logic Devices |
5/28/2018 |
134-222 | 134-222 | 5. Architecture of FPGAs |
7/3/2018 |
223-246 | 223-246 | 6. Design Flow |
7/10/2018 |
247-263 | 247-263 | 7. Partially Dynamic Reconfiguration |
7/10/2018 |
Exercise Sheets
Exercise | Contents | Submission Date | |
Sheet 1 | Combinatorial Circuits / FSM | 5/1/2018 | |
Sheet 2 | Sequential Circuts / FSM | 4/26/2018 during the exercise | |
Sheet 3 | modelsim.zip | Modelsim installation | 5/8/2018 |
Sheet 4 | VHDL basics | 5/15/2018 | |
Sheet 5 | exercise.zip | VHDL + testbenches | 5/29/2018 |
Sheet 6 | exercise.zip | VHDL Packages + Physical Types | 6/12/2018 |
Sheet 7 | PLA + Virtex-5 LUT | 6/19/2018 | |
Sheet 8 | exercise.zip | Fast Carry Chains + Virtex-5 | 6/19/2018 |
Sheet 9 | DSP Slices | 7/03/2018 | |
Sheet 10 | Place and Route | 7/10/2018 |
Resources
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Virtex-5 FPGA Packaging and Pinout Specification
Virtex-5 FPGA XtremeDSP Design Considerations
Virtex-5 Libraries Guide for HDL Designs